Semiconductor devices often comprise functional layers which are formed epitaxially. Epitaxial deposition allows the formation of a single-crystalline material and is thus a versatile method which is used for the manufacture of a variety of power semiconductor devices such as such SiC JFETs (Silicon Carbide Junction Field Effect Transistors). During deposition, the deposited material can be doped so that a subsequent doping by implantation is often not required.
The epitaxial deposition, however, requires delicate handling and is rather expensive. Despite advanced control systems and adopted deposition chambers, fluctuations of both the thickness and the doping concentration may occur which could adversely affect the performance of the thus manufactured semiconductor devices. For example, the pinch-off voltage of a JFET is determined by the geometry and doping concentration of its channel. Variation of any of these parameters changes the pinch-off voltage to unwanted values and can alter the saturation characteristics of the JFET. Further, a plurality of separate epitaxial deposition steps is required for forming a JFET. In view of this, there is an ongoing desire to improve the manufacturing procedures to obtain high quality devices with well defined and uniform characteristics.